1. Field of the Invention
The present invention relates to a semiconductor device which features copper wiring layers having metal capping layers formed thereon, and a method for manufacturing such a semiconductor device.
2. Description of the Related Art
In a process of production of semiconductor devices, semiconductor elements, such as transistors, resistors, capacitors and so on, are produced in a semiconductor substrate, and then a multi-layered wiring structure is formed on the semiconductor substrate. The multi-layered wiring structure includes a local multi-layered wiring section formed on the semiconductor substrate, and a global multi-layered wiring section formed on the local multi-layered wiring section.
The local multi-layered wiring section includes a plurality of insulating interlayers, a plurality of wiring pattern layers each formed on one of the insulating interlayers, a plurality of groups of via plugs each group formed in one of the insulating interlayers to establish electrical connections between opposing ones of the two wiring pattern layers. The wiring pattern layers serve as power supply lines, ground lines and signal lines.
Usually, the power supply lines and the ground lines are arranged in parallel at a given pitch in a power/ground line area defined on the insulating interlayers, and the signal lines are arranged in parallel at a given pitch in a signal line area defined on the corresponding insulating interlayers. The power supply lines and the ground lines are wider than the signal lines, and a space or pitch between two adjacent ones of the power/ground lines is larger than a space or pitch between two adjacent ones of the signal lines.
The global multi-layered wiring section is constituted in substantially the same manner as the local multi-layered wiring section, but the power/ground lines and signal lines in the global multi-layered wiring section are wider than those of the local multi-layered wiring section.
With the advance of miniaturization and integration of semiconductor devices, the wiring pattern layers become smaller, and thus the signal lines become narrower, resulting in delay of signal propagation in the narrowed wiring lines, due to a parasitic resistance of the signal lines themselves and a parasitic capacitance involved in the signal lines.
In order to improve the delay of the signal propagation, it has been proposed that copper be used for the wiring pattern layers as a substitute for aluminum, which is conventionally used for the wiring pattern layers. Also, the use of copper is advantageous in that the copper wiring pattern layers exhibit a superior anti-electromigration (EM) characteristic in comparison with that of the aluminum wiring pattern layers.
Nevertheless, when the miniaturization and integration of semiconductor devices is further advanced, the copper wiring pattern layers become increasingly smaller, so that a non-neglectable electromigration may occur in the copper wiring pattern layers. Also, as a problem peculiar to fine copper wiring layers, there is a stress induced voiding (SIV) problem, in which voids are produced in roots of the via plugs formed in the insulating interlayers, due to thermal stresses to which the copper wiring layers are subjected. Namely, in the copper wiring layers, it is necessary to take an anti-SIV characteristic into consideration.
In order to improve both the anti-electromigration characteristic and the anti-SIV characteristic in the copper wiring layers, it has been proposed that surfaces of the copper wiring layers are coated with metal capping layers which are composed of CoWP, CoSnP or CoP, as disclosed in, for example, JP-2003-505882-A. However, when the metal capping layers are formed on the fine copper wiring layers, featuring the minimum line width, included in the local multi-layered wiring section, the formation of the metal capping layers on the fine copper wiring layers is liable to be exceeded, resulting in occurrence of short circuits between the fine copper wiring layers, as stated in detail hereinafter.